1. Field of the Invention
The present invention relates to a signal transmission device that transmits signals fed thereto to another device through a transformer.
2. Description of the Prior Art
As an example of a conventional signal transmission device, a terminal adapter, which is needed to connect terminal equipment such as a personal computer to an ISDN (integrated services digital network) line, will be described. FIG. 4 is a diagram showing an outline of an example of a configuration that permits connection between an ISDN line and terminal equipment. A similar configuration is disclosed in Japanese Patent Application Laid-Open No. H11-330937.
As shown in this figure, to connect terminal equipment TE to an ISDN line, it is necessary to use a terminal adapter 10 that converts the signals fed thereto from the terminal equipment TE into a signal format adapted for the ISDN line and a digital service unit 20 (hereinafter referred to as the xe2x80x9cDSU 20xe2x80x9d) that serves as a terminal interface device by converting the signals from a telephone company, which are adapted for network transfer, to signals adapted for distribution inside a household so as to be ready for bus-based wiring.
The interface I/F between the terminal adapter 10 and the DSU 20 is composed of a transformer employing coils, and the ISDN standard sets strict requirements regarding overshoots and undershoots that occur at such a signal conversion point.
FIG. 5 is a diagram showing an outline of the configuration of an example of a conventional terminal adapter 10. A logic circuit 11 that converts the signals from the terminal equipment TE into a signal format adapted for the ISDN line is connected through an output circuit 12 to the primary coil L1 of the interface I/F. The output circuit 12 feeds the coil L1 with current based on the signals output from the logic circuit 11, and the output stage of the output circuit 12 is composed of a P-channel MOS transistor QH1 and an N-channel MOS transistor QL1 that are connected in series between a supply voltage line and a GND (ground) line and a P-channel MOS transistor QH2 and an N-channel MOS transistor QL2 that are similarly connected in series between the supply voltage line and the GND line.
The drains of the transistors QH1 and QL1 are connected together through a resistor R1 to one end of the coil L1, and the drains of the transistors QH2 and QL2 are connected together through a resistor R2 to the other end of the coil L1. The sources of the transistors QH1 and QH2 are connected through constant-current source circuits CC1 and CC2, respectively, to the supply voltage line, and the sources of the transistors QL1 and QL2 are connected to the GND line. The resistors R1 and R2 both serve to limit the current that flows through the coil L1, and the constant-current source circuits CC1 and CC2 both serve to limit transient fluctuations in the current that flows through the coil L1.
The gate of the transistor QH1 is connected directly to a first output terminal O1 of the logic circuit 11, and the gate of the transistor QH2 is connected directly to a second output terminal O2 of the logic circuit 11. The gate of the transistor QL1 is connected through a timing adjustment circuit T1 to the first output terminal O1, and the gate of the transistor QL2 is connected through a timing adjustment circuit T2 to the second output terminal O2.
Here, when the logic circuit 11 outputs at its first and second output terminals O1 and O2 a H (high) level and a L (low) level, respectively, the transistors QH1 and QL2 are off, and the transistors QL1 and QH2 are on. Accordingly, the constant current produced by the constant-current source circuit CC2 flows through the transistor QH2, resistor R2, coil L1, resistor R1, and transistor QL1 to the GND line, and thus the voltage F appearing across the coil L2 is positive (in a H state).
By contrast, when the logic circuit 11 outputs at its first and second output terminals O1 and O2 a L level and a H level, respectively, the transistors QH1 and QL2 are on, and the transistors QL1 and QH2 are off. Accordingly, the constant current produced by the constant-current source circuit CC1 flows through the transistor QH1, resistor R1, coil L1, resistor R2, and transistor QL2 to the GND line, and thus the voltage F appearing across the coil L2 is negative (in a L state).
When the logic circuit 11 outputs a L level at both of its first and second output terminals O1 and O2, no current flows through the coil L1, and thus no voltage appears across the coil L2 (in a M (middle) state). It never occurs that the logic circuit 11 outputs a H level at both of its first and second output terminals O1 and O2.
Now, the operation of the timing adjustment circuits T1 and T2 mentioned above will be described. The timing adjustment circuits T1 and T2 are provided for the purpose of reducing the overshoots and undershoots that occur in the square wave appearing across the coil L1. The timing adjustment circuits T1 and T2 are so configured that, when the input thereto rises to a H level, they turn their output to a H level irrespective of a clock CLK but, when the input drops to a L level, they turn their output to a L level after counting a predetermined number of pulses in the clock CLK.
For example, in a case where the timing adjustment circuits T1 and T2 receive, as their clock CLK, the clock signal (for example, having a frequency of 6 MHz) used for the logic circuit 11, and are so configured that they turn their output to a L level in synchronism with the second rising edge in the clock CLK, the timing adjustment circuits T1 and T2 produce a delay time t of about 170 nanoseconds.
In this way, the timing adjustment circuits T1 and T2 serve to shift level switching points of the digital signals that are applied to the gates of the transistors QL1 and QL2, and desired timing adjustment can easily be achieved by using, for example, flip-flops. Thus, it is possible to produce a short delay stably, without slowing down the data transfer rate.
FIG. 6 is a timing chart showing the waveforms of signals observed at relevant points in the terminal adapter 10. In this figure, reference symbols A, B, C, and D indicate the digital signals that are applied to the gates of the transistors QH1, QL1, QH2, and QL2, respectively, and reference symbol F indicates the voltage that appears across the coil L2.
As described previously, in the terminal adapter 10 configured as described above, as shown in the figure, level switching points of the digital signals B and D applied to the gates of the corresponding transistors are shifted by the timing adjustment circuits T1 and T2. More precisely, when the individual transistors are switched between on and off, any transistor that has been receiving current from the coil L1 up to that moment is switched from on to off with a delay of t from the time point at which the other transistors are switched between on and off.
In the terminal adapter 10 configured as described above, it is possible, indeed, to reduce transient fluctuations in the current flowing through the coil L1 and thereby reduce the back electromotive force induced by the inductance of the coil. As a result, it is possible to reduce the overshoots OS and undershoots US (indicated by a dash-and-dot line in the figure) that occur in the square wave appearing across the coil L2.
However, in the terminal adapter 10 configured as described above, on occasions when the levels of the two signals output from the logic circuit 11 are switched in opposite directions, i.e. when one signal turns from a H level to a L level and simultaneously the other signal turns from a L level to a H level, the square wave appearing across the coil L2 may be distorted as indicated by reference symbol S in FIG. 6. This problem arises when the delay time t produced by the timing adjustment circuits T1 and T2 is too long, and the signal INFO1 on an ISDN line or the like is particularly prone to such distortion.
Distortion as described above of the square wave appearing across the coil L2 leads to increased jitter, which not only degrades signal transmission quality but also, in some cases, brings signals out of synchronism, making correct signal transmission impossible.
An object of the present invention is to provide a signal transmission device that can reduce overshoots and undershoots without distorting the waveform of a square wave appearing across a coil constituting a transformer.
To achieve the above object, according to the present invention, a signal transmission device is provided with: a transformer having primary and secondary coils; switching devices that are connected in series between two different potentials and that are turned on/off individually according to a control signal; a coil driving circuit that switches the direction of the current flowing through the primary coil by controlling the switching devices; a timing adjustment circuit that delays the timing with which, of all the switching devices, the one which has been receiving current up to now is turned off relative to the timing with which the other switching devices are turned on or off; and a waveform adjustment circuit that controls the delay time produced by the timing adjustment circuit according to changes in the state of the control signal.